The waveform of a digital signal that is outputted by a transmitter deteriorates while being transmitted from the transmitter to a receiver via a transmission channel. Therefore, a clock signal and data must be restored on the receiver side. Clock data restoration devices for performing such restoration are disclosed in, for instance, Patent documents 1 and 2.
In the devices disclosed in the documents, each bit data is detected at three timings in consideration of fluctuations in data transition time in the deteriorated-waveform digital signal. Among the three timings at which each bit data is detected, the first timing is set in the vicinity of an initial time of a data stable period of the bit, the second timing is set in the vicinity of a terminal time of the data stable period of the bit, and the third timing is set at a central time between the first timing and the second timing.
In the device disclosed in Patent document 1, the clock signal is restored by adjusting the timings in such a manner that the data detected at the three timings match, for each bit. Data is restored then by detecting each bit data at the central third timing.
In the device disclosed in Patent document 2, meanwhile, the clock signal is restored by adjusting the timings in such a manner that the bit error rates at the first timing and the second timing (i.e. the ratios by which data detected at each timing differs from the data detected at a central third timing) are equal to each other and lie within an initial set range. Data is restored then by detecting the data of each bit at the central third timing.    Patent document 1: Japanese Patent Application Laid-open No. 7-221800    Patent document 2: Published Japanese translation of a PCT application No. 2004-507963